运用VHDL设计1个模为24的8421BCD码加法计数器

运用VHDL设计1个模为24的8421BCD码加法计数器

奉献一个原创的
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
ENTITY bcd_cnt_1r0 IS
GENERIC(num_bit :INTEGER := 2;
modulo :INTEGER := 24);
PORT(clk :IN STD_LOGIC;
rst :IN STD_LOGIC;
cnt_en :IN STD_LOGIC;
bcd_out :OUT STD_LOGIC_VECTOR(num_bit * 4 - 1 DOWNTO 0));
END bcd_cnt_1r0;
ARCHITECTURE rtl OF bcd_cnt_1r0 IS
CONSTANT ONES :STD_LOGIC_VECTOR(num_bit DOWNTO 0) := (OTHERS=>'1');
FUNCTION dec2unsigned (dec_val:INTEGER; dec_bit :INTEGER) RETURN UNSIGNED IS
VARIABLE result:UNSIGNED(dec_bit*4 - 1 DOWNTO 0);
VARIABLE tmp :INTEGER := dec_val;
VARIABLE tmp2 :INTEGER := 0;
BEGIN
FOR i IN 1 TO dec_bit LOOP
tmp2 := (tmp/10);
result(i*4-1 DOWNTO (i-1)*4) := TO_UNSIGNED(tmp - tmp2 * 10,4);
tmp := tmp2;
END LOOP;
RETURN result;
END dec2unsigned;
CONSTANT unsign_modulo :UNSIGNED(num_bit * 4 - 1 DOWNTO 0) := dec2unsigned(modulo,num_bit);
SIGNAL next_cnt :UNSIGNED(num_bit * 4 - 1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL curr_cnt :UNSIGNED(num_bit * 4 - 1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL carray_in :STD_LOGIC_VECTOR(num_bit DOWNTO 0):=(OTHERS=>'0');
TYPE dec_array_type IS ARRAY(num_bit-1 DOWNTO 0) OF UNSIGNED(3 DOWNTO 0);
SIGNAL debug_dec_cnt_bit :dec_array_type :=(OTHERS=>(OTHERS=>'0'));
BEGIN
reg_proc:PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
IF rst = '1' THEN
curr_cnt '0');
ELSE
IF cnt_en = '1' THEN
IF next_cnt = unsign_modulo THEN
curr_cnt '0');
ELSE
curr_cnt