作业帮求单片机 英文参考文献
来源：学生作业帮 编辑：作业帮 分类：英语作业 时间：2024/11/05 14:36:41
求单片机 英文参考文献
不要给我文章,我要的是书名,作者,出版社,出版时间和第几页那种
不要给我文章,我要的是书名,作者,出版社,出版时间和第几页那种
【1】V.Yu.Teplov,A.V.Anisimov.Thermostatting System Using a Single-Chip Microcomputer and Thermoelectric Modules Based on the Peltier Effect[J] ,2002
【2】 Yeager Brent.How to troubleshoot your electronic scale[J]..Powder and Bulk Engineering.1995
【3】Meehan Joanne,Muir Lindsey.SCM in Merseyside SMEs:Benefits and barriers[J]..TQM Journal.2008
看着有用的用吧,单片机很多东西,也不知道你的具体是哪个方面的.
再问： 关于测量一块的，你给的三个都不好，能不能换一下。。。。。。
再答： 你把你的论文题目给我，别总给我模糊的东西，费劲半天，也没合适的
再问： 数字电压表
再答： [1] Behzad Razavi.Design of Analog CMOS Integrated Circuits[M]. . 2001 [2] Rhee W.Design of high-performance CMOS charge pumps inphase-locked loops. IEEE International Symposium on Cir-cuits and Systems. 1999 [3] Todd Charles Weigandt.Low-phase-noise,low-timing-jitter design techniques for delay cell based VCOs and frequency synthesizers[C]//PHDthesis. . 1998 [4] George Lee,Karina Ng,Edmond Kwang.Design of ring oscillator based voltage controlled oscillator. Project Final Report[R]. 2005 [5] T. C. Weigandt,B. Kim,and P. R. Gray.Analysis of Timing Jitter in CMOS Ring Oscillators. IEEE International Symposium on Circuits and Systems. 1994 [6] Nonis R,Da Dalt N,Palestri P,et al.Modeling,design andcharacterization of a new low-jitter analog dual tuning LC-VCOPLL architecture[J]. IEEE Journal of Solid State Circuits. 2005 [7] Lim Kyoohyun,Park Chanhong,Kim Dalsoo,et al.A low-noise phase-locked loop design by loop bandwidth optimization. IEEE Journal of SolidState Circuits. 2000 [8] Boerstler D W.A low-jitter PLL clock generator for microprocessors with lock range of 340 ~ 612MHz. IEEE Journal of Solid State Circuits. 1999 [9] Lee Jri.High-Speed Circuit Designs for Transmittersin Broad-band Data Links. IEEE Journal of Solid-State Circuits[J]. 2006 [10] Adrian Maxim,Ramin K.Poorfard,Richard A.Johnson,et al.A Fully Integrated 0.13-μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. IEEE Journal of Solid State Circuits. 2007 看着有用的用吧，再不行我就没招了，你自己去google搜索吧，英文关键词加点pdf
【2】 Yeager Brent.How to troubleshoot your electronic scale[J]..Powder and Bulk Engineering.1995
【3】Meehan Joanne,Muir Lindsey.SCM in Merseyside SMEs:Benefits and barriers[J]..TQM Journal.2008
看着有用的用吧,单片机很多东西,也不知道你的具体是哪个方面的.
再问： 关于测量一块的，你给的三个都不好，能不能换一下。。。。。。
再答： 你把你的论文题目给我，别总给我模糊的东西，费劲半天，也没合适的
再问： 数字电压表
再答： [1] Behzad Razavi.Design of Analog CMOS Integrated Circuits[M]. . 2001 [2] Rhee W.Design of high-performance CMOS charge pumps inphase-locked loops. IEEE International Symposium on Cir-cuits and Systems. 1999 [3] Todd Charles Weigandt.Low-phase-noise,low-timing-jitter design techniques for delay cell based VCOs and frequency synthesizers[C]//PHDthesis. . 1998 [4] George Lee,Karina Ng,Edmond Kwang.Design of ring oscillator based voltage controlled oscillator. Project Final Report[R]. 2005 [5] T. C. Weigandt,B. Kim,and P. R. Gray.Analysis of Timing Jitter in CMOS Ring Oscillators. IEEE International Symposium on Circuits and Systems. 1994 [6] Nonis R,Da Dalt N,Palestri P,et al.Modeling,design andcharacterization of a new low-jitter analog dual tuning LC-VCOPLL architecture[J]. IEEE Journal of Solid State Circuits. 2005 [7] Lim Kyoohyun,Park Chanhong,Kim Dalsoo,et al.A low-noise phase-locked loop design by loop bandwidth optimization. IEEE Journal of SolidState Circuits. 2000 [8] Boerstler D W.A low-jitter PLL clock generator for microprocessors with lock range of 340 ~ 612MHz. IEEE Journal of Solid State Circuits. 1999 [9] Lee Jri.High-Speed Circuit Designs for Transmittersin Broad-band Data Links. IEEE Journal of Solid-State Circuits[J]. 2006 [10] Adrian Maxim,Ramin K.Poorfard,Richard A.Johnson,et al.A Fully Integrated 0.13-μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer. IEEE Journal of Solid State Circuits. 2007 看着有用的用吧，再不行我就没招了，你自己去google搜索吧，英文关键词加点pdf